1. Field of the Invention
This invention relates to improved field effect transistor structures and, more particularly, to a structure and method for minimizing parasitic inversion.
2. Description of the Prior Art
The metal oxide semiconductor field effect transistor is a well-known type of device operating by flow of majority charge carriers. The field effect transistor has spaced source and drain regions of low resistivity doped with a first type impurity for semiconductors in a single crystal semiconductor material having a high resistivity due to a low concentration of an opposite second type background impurity for semiconductors. A conduction channel is thereby provided between the source and drain regions. The field effect transistor includes a control or gate structure for controlling the flow of majority charge carriers through the channel consisting of a thin film of insulation adjacent the channel and a metal or other conductive gate electrode over the insulating film. Appropriate circuit connections are made to the source, drain and gate electrodes.
The relative simplicity of fabrication and its circuit characteristics make field effect transistors very attractive for use in integrated circuit devices of the monolithic semiconductor type, particularly for computer applications.
During operation of integrated circuit devices utilizing FET's, voltages and currents are conducted by means of interconnections provided between the devices. The interconnection system consisting of one or more metallurgy stripes is separated from the semiconductor body by a relatively thick layer of field insulation. The voltages in the interconnection system cause electrical fields and charges to build up in, on, and about the surface of the substrate and the overlying protective field insulation layer, which in turn give rise to unwanted parasitic conduction paths along and near the device surface. Parasitic inversion of the field regions of field effect transistors in integrated circuit devices is a common and serious problem, particularly in N channel type devices, which leads to current leakage. When parasitic conduction paths are allowed to extend from one active device to another, unwanted shorts and even catastrophic failures result. To control parasitic inversion, various methods are known in the prior art to control and prevent the spread of unwanted inversion. One technique is to provide special regions of increased conductivity at selected locations within the substrate in order to interrupt the inversion paths. These regions, usually formed by diffusion, are known as channel stops and are of the same conductivity as the substrate but with a higher surface concentration. Although satisfactory for some applications, the channel stop regions take up a relatively large portion of the available surface area thereby imposing serious restraints on the degree of miniaturization that can be achieved. For high density integrated circuits or complex arrays in which many field effect transistors are fabricated together in a small area on the substrate, the channel stop solution is unsatisfactory. Since parasitic inversion of the substrate surface is in general inversely proportional to insulating layer thickness, unwanted parasitic inversion can also be reduced by increasing the thickness of the insulating layer. However, it is frequently impractical to increase the protective layer thickness to the extent necessary to control parasitic inversion due to fabricating difficulties, for example, the difficulty of subtractively etching a relatively thick layer to very small geometries. Also, thick protective layers may develop contamination problems causing the electrical characteristics of the device to drift over a period of time. Another technique that has been suggested for controlling inversion is to imbed conductive layers in the field dielectric beneath the interconnection layers that are connected to the body of the device. This technique also has its limitations since it requires additional fabricating process steps demanding additional masking, etching and aligning steps which, in general, decrease the overall yield of the device.
Another technique which has been suggested is to increase the impurity concentration in the field regions by a diffusion or ion bombardment. The techniques known to the prior art for increasing the impurity concentration require additional masking and etching steps, as well as heating steps which cause device yield loss due to the probability of inherent misalignments and movement of the diffusions within the device.
A means for controlling unwanted inversion along the substrate surface of an FET device is therefore needed that does not reduce available surface area, does not interfere with subsequent processing steps, does not increase the oxide thickness above a practical limit, and does not increase the turn-on voltage.